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1 www.semtech.com SC4605 low input, high efficiency synchronous, step down controller power management revision: october 14, 2004 description features applications typical application circuit ? bicmos voltage mode pwm controller ? 2.8v to 5.5v input voltage range ? output voltages as low as 0.8v ? +/-1% reference accuracy ? sleep mode (icc = 10a typ) ? lossless adjustable short circuit current limiting ? combination pulse by pulse & hiccup mode current limit ? high efficiency synchronous switching ? 0% to 97% duty cycle range ? 1a peak current driver ? 10-pin msop package ? distributed power architecture ? servers/workstations ? local microprocessor core power supplies ? dsp and i/o power supplies ? battery powered applications ? telecommunications equipment ? data processing applications the SC4605 is a voltage mode step down (buck) regula- tor controller that provides accurate high efficiency power conversion from a input supply range of 2.8v to 5.5v. a high level of integration reduces external component count, and makes it suitable for low voltage applications where cost, size and efficiency are critical. the SC4605 drives external n-channel mosfets with 1a peak current. a non-overlap protection is provided for the gate drive signals to prevent shoot through of the mosfet pair. the voltage drop across the high side mosfet during its conduction is sensed for lossless short circuit current limiting. the quiescent supply current in sleep mode is typically lower than 10 a. a 1.8ms soft start is internally provided to prevent output voltage overshoot during start-up. the SC4605 is an ideal choice for 3.3v, 5v or other low input supply systems. it?s available in 10 pin msop pack- age. * external components can be modified to provide a vout as low as 0.8v. r3 c3 4.7u c2 2.2n c6 330u r1 14.3k c1 180p c14 0.1u vin = 2.8v - 5.5v d2 l1 1.8u c5 22u c4 22u vout = 1.5v (as low as 0.8v * ) / 12a c71 1u m1 c10 220u m2 c12 22u c9 4.7n r8 200 r7 10k r9 11.5k c20 470pf u1 SC4605 vcc 2 iset 3 comp 4 fset 5 bst 1 drvh 10 drvl 8 vsense 6 gnd 7 phase 9 c11 22u r13 1 * external components can be modified to provide a vout as low as 0.8v. r3 c3 4.7u c2 2.2n c6 330u r1 14.3k c1 180p c14 0.1u vin = 2.8v - 5.5v d2 l1 1.8u c5 22u c4 22u vout = 1.5v (as low as 0.8v * ) / 12a c71 1u m1 c10 220u m2 c12 22u c9 4.7n r8 200 r7 10k r9 11.5k c20 470pf u1 SC4605 vcc 2 iset 3 comp 4 fset 5 bst 1 drvh 10 drvl 8 vsense 6 gnd 7 phase 9 c11 22u r13 1 fs/sync
2 ? 2004 semtech corp. www.semtech.com SC4605 power management absolute maximum ratings electrical characteristics r e t e m a r a ps n o i t i d n o c t s e tn i mp y tx a mt i n u l l a r e v o e g a t l o v y l p p u s 8 . 25 . 5v p e e l s , t n e r r u c y l p p u sv 0 = c n y s / s f0 15 1a s a i b , t n e r r u c y l p p u sv c c =v 5 . 513a m d l o h s e r h t n o - n r u t c c v 7 . 28 . 2v s i s e r e t s y h f f o - n r u t c c v 5 2 1v m r e i f i l p m a r o r r e e g a t l o v t u p n i ) e c n e r e f e r l a n r e t n i ( t a c 5 2 =2 9 7 . 08 . 08 0 8 . 0 v v c c t , v 5 . 5 ~ v 8 . 2 = a c 5 2 =8 8 7 . 08 . 02 1 8 . 0 e r u t a r e p m e t6 8 7 . 08 . 04 1 8 . 0 t n e r r u c s a i b e s n e s v 5 2a n n i a g p o o l n e p o ) 1 ( v p m o c v 5 . 2 o t 5 . 0 =0 8b d h t d i w d n a b n i a g y t i n u ) 1 ( 4z h m e t a r w e l s ) 1 ( 2s / v h g i h t u o vi p m o c a m 2 - =v c c 5 . 0 -v c c 2 . 0 -v w o l t u o vi p m o c a m 2 =1 . 05 2 . 0v r e t e m a r a pl o b m y sm u m i x a ms t i n u v ( e g a t l o v y l p p u s c c )7v s t n e r r u c ) l v r d , h v r d ( s r e v i r d t u p t u o s u o u n i t n o c k a e p 5 2 . 0 - / +a 0 0 . 1 - / +a ) t e s i , c n y s / s f , p m o c , e s n e s v ( s t u p n i 7 o t 3 . 0 -v e s a h p 5 . 5 o t 3 . 0 -v s n 0 0 1 < e s l u p t e s l u p e s a h p 7 o t 2 -v e g n a r e r u t a r e p m e t t n e i b m a g n i t a r e p ot a 5 8 + o t 0 4 -c e g n a r e r u t a r e p m e t e g a r o t st g t s 0 5 1 + o t 5 6 -c e g n a r e r u t a r e p m e t n o i t c n u jt j 0 5 1 + o t 5 5 -c . c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e lt d a e l 0 0 3 +c all voltages with respect to gnd. currents are positive into, negative out of the specified terminal. unless otherwise specified, vcc = 5v, ct = 470pf, t a = -40c to 85c, t a = t j . exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied.
3 ? 2004 semtech corp. www.semtech.com SC4605 power management electrical characteristics (cont.) r e t e m a r a ps n o i t i d n o c t s e tn i mp y tx a mt i n u r o t a l l i c s o y c a r u c c a l a i t i n it a c 5 2 =5 5 20 0 35 4 3z h k y c n e u q e r f n o i t a r e p o m u m i n i m ) 1 ( 0 0 1z h k y c n e u q e r f n o i t a r e p o m u m i x a m ) 1 ( 0 0 6z h k y e l l a v o t k a e p p m a r ) 1 ( 5 . 1v e g a t l o v k a e p p m a r ) 1 ( 0 . 2v e g a t l o v y e l l a v p m a r ) 1 ( 5 . 0v t i m i l t n e r r u c , t r a t s t f o s , p e e l s d l o h s e r h t p e e l ss f t a d e r u s a e m2 . 0v e m i t t r a t s t f o s ) 1 ( 8 . 1s m t n e r r u c s a i b t e s it j c 5 2 =3 4 -0 5 -7 5 -a e m i t k n a l b t i m i l t n e r r u c ) 1 ( 0 5 1s n e v i r d e t a g e l c y c y t u d 07 9% ) h v r d ( e c r u o s k a e p ) 2 ( i , v 5 = s g v e c r u o s a m 0 0 1 =3 ? ) h v r d ( k n i s k a e p ) 2 ( i , v 5 = s g v k n i s a m 0 0 1 =3 ? ) l v r d ( e c r u o s k a e p ) 2 ( i , v 5 = s g v e c r u o s a m 0 0 1 =3 ? ) l v r d ( k n i s k a e p ) 2 ( i , v 5 = s g v k n i s a m 0 0 1 =3 ? e m i t e s i r t u p t u o ) 2 ( c , v 5 = s g v t u o f n 7 . 4 =5 3s n e m i t l l a f t u p t u o ) 2 ( c , v 5 = s g v t u o f n 7 . 4 =5 3s n p a l r e v o - n o n m u m i n i m ) 1 ( 0 30 4s n notes: (1). guaranteed by design. (2). guaranteed by characterization. (3) this device is esd sensitive. use of standard esd handling precautions is required. unless otherwise specified, vcc = 5v, ct = 470pf, t a = -40c to 85c, t a = t j .
4 ? 2004 semtech corp. www.semtech.com SC4605 power management ordering information pin descriptions r e b m u n t r a p ) 1 ( e c i v e d r t s m i 5 0 6 4 c s 0 1 - p o s m t r t s m i 5 0 6 4 c s ) 2 ( vcc: positive supply rail for the ic. bypass this pin to gnd with a 0.1 to 4.7f low esl/esr ceramic capaci- tor. gnd: all voltages are measured with respect to this pin. all bypass and timing capacitors connected to gnd should have leads as short and direct as possible. fs/sync: a capacitor from fs pin to gnd sets the pwm oscillator frequency. use a high quality ceramic capacitor with low esl and esr for best result. a minimum capaci- tor value of 200pf ensures good accuracy and less sus- ceptibility to circuit layout parasitics. when the fs is pulled and held below 0.2v, its sleep mode operation is invoked. the sleepmode supply current is 10a typical. the oscil- lator and pwm are designed to provide practical opera- tion up to 600khz. in synchronous mode operation, a low value resistor has to be connected between ground and the timing capacitor. an external clock is then feed into the resistor capacitor junction to override the inter- nal clock. vsense: this pin is the inverting input of the voltage amplifier and serves as the output voltage feedback point for the buck converter. it senses the output voltage through an external divider. comp: this is the output of the voltage amplifier. the voltage at this output is inverted internally and connected to the non-inverting input of the pwm comparator. a lead- lag network around the voltage amplifier compensates for the two pole lc filter characteristic inherent to voltage mode control and is required in order to optimize the dynamic performance of the voltage mode control loop. iset / phase: phase is connected to the junction be- tween the two external power mosfet transistors. the voltage drop across the high side mosfet during its con- duction is compared with the voltage drop generated by the internal 50a current source and the external cur- rent limit resistor connected between phase and vin, and forms the current limit comparator and logic sets the pwm latch and terminates the output pulse. if the converter output voltage drops below 68.75% of its nomi- nal voltage, the controller stops switching and goes through a soft start sequence. this prevents excess power dissipation in the low side mosfet during a short circuit. the current limit threshold is set by the external resistor between vcc and iset. bst: this pin connects the external charge pump, and powers the high side mosfet gate drive. drvh, drvl: the output drivers are rated for 1a peak currents. the pwm circuitry provides complementary drive signals to the output stages. the cross conduction of the external mosfets is prevented by monitoring the voltage on the driver pins of the mosfet pair in conjunc- tion with a time delay optimized for fet turn-off charac- teristics. notes: (1) only available in tape and reel packaging. a reel contains 2500 devices. (2) lead free product. this product is fully weee and rohs compliant. pin configuration 1 2 3 4 drvh bst top view (msop-10) 7 8 9 10 phase vcc drvl iset gnd comp 5 6 vsense fs/sync
5 ? 2004 semtech corp. www.semtech.com SC4605 power management block diagram marking information yyww = datecode (example: 0012) xxxx = semtech lot # (example: e901 xxxx 01-1)
6 ? 2004 semtech corp. www.semtech.com SC4605 power management applications information enable pulling and holding the fs/sync pin below 0.2v initial- izes the sleep mode of the SC4605 with its typical sleep mode supply current of 10 a. during the sleep mode, the high side and low side mosfets are turned off and the internal soft start voltage is held low. oscillator the oscillator uses an external capacitor between fs and gnd to set the oscillation frequency. the ramp wave- form is a triangle at the pwm frequency with a peak volt- age of 2v and a valley voltage of 0.5v. the pwm duty ratio is limited to a maximum of 97%, which allows the bootstrap capacitor to be charged during each cycle. the capacitor tolerance adds to the accuracy of the oscilla- tor frequency. the approximate operating frequency is determined by the external capacitor connected to the fs/sync pin as shown below: t 4 s c 10 55 . 1 f ? ? = in its synchronous mode, a low value resistor needs to be connected between ground and the frequency set- ting capacitor, ct. then an external clock connects to the junction of the resistor and the capacitor to activate its synchronous mode. the frequency of the clock can be used up to 700khz. this external clock signal should have a duty cycle from 5% to 10% and the peak voltage at the junction from the clock signal should be about 0.2v. uvlo when the fs/sync pin is not pulled and held below 0.2v, the voltage on the vcc pin determines the operation of the SC4605. as vcc increases during start up, the uvlo block senses vcc and keeps the high side and low side mosfets off and the internal soft start voltage low until vcc reaches 2.8v. if no faults are present, the SC4605 will initiate a soft start when vcc exceeds 2.8v. a hyster- esis (150mv) in the uvlo comparator provides noise immunity during its start up. soft start the soft start function is required for step down control- lers to prevent excess inrush current through the dc bus during start up. generally this can be done by sourcing a controlled current into a timing capacitor and then using the voltage across this capacitor to slowly ramp up the error amp reference. the closed loop creates narrow width driver pulses while the output voltage is low and allows these pulses to increase to their steady state duty cycle as the output voltage reaches its regulated value. with this, the inrush current from the input side is con- trolled. the duration of the soft start in the SC4605 is controlled by an internal timing circuit which is used dur- ing start up and over current to set the hiccup time. the soft start time can be calculated by: s start _ soft f 720 t = as can be seen here, the soft start time is switching fre- quency dependant. for example, if fs = 300khz, tsoft_start = 720/300k = 2.4ms. but if fs = 600khz, tsoft_start = 720/600k = 1.2ms. the SC4605 implements its soft start by ramping up the error amplifier reference voltage providing a controlled slew rate of the output voltage, then preventing over- shoot and limiting inrush current during its start up. over current protection over current protection for the SC4605 is implemented by detecting the voltage drop of the high side n-mosfet during its conduction, also known as high side rds(on) detection. this loss-less detection eliminates the sense resistor and its loss. the overall efficiency is improved and the number of components and cost of the con- verter are reduced. rds(on) sensing is by default inac- curate and is mainly used to protect the power supply during a fault case. the over current trigger point will vary from unit to unit as the rds(on) of n-mosfet var- ies. even for the same unit, the over current trigger point will vary as the junction temperature of n-mosfet var- ies. the SC4605 provides a built-in 50 a current source, which is combined with rset (connected between vcc and iset) to determine the current limit threshold. the value of rset can be properly selected according to the desired current limit point imax and the internal 50 a pull down current available on the iset pin based on the following expression:
7 ? 2004 semtech corp. www.semtech.com SC4605 power management applications information (cont.) a 50 r i r ) on ( ds max set ? = kelvin sensing connections should be used at the drain and source of n-mosfet. r set needs to be adjusted if the input of the application changes significantly, say from 3.3v to 5v for the same load and same output voltage. a 0.1 a ceramic capacitor paralled to this resistor should be used to decouple the noise. the rds(on) sensing used in the SC4605 has an addi- tional feature that enhances the performance of the over current protection. because the rds(on) has a positive temperature coefficient, the 50 a current source has a positive coefficient of about 0.17%/c providing first order correction for current sensing vs temperature. this com- pensation depends on the high amount of thermal trans- ferring that typically exists between the high side n- mosfet and the SC4605 due to the compact layout of the power supply. when the converter detects an over current condition (i > imax) as shown in figure 1, the first action the SC4605 takes is to enter the cycle by cycle protection mode (point b to point c), which responds to minor over current cases. then the output voltage is monitored. if the over current and low output voltage (set at 68.75% of nominal out- put voltage) occur at the same time, the hiccup mode operation (point c to point d) of the SC4605 is invoked and the internal soft start capacitor is discharged. this is like a typical soft start cycle. i max nom o v ? ? 6875 . 0 nom o v ? o v o i a b d c nom o v ? ? 125 . 0 figure 1. over current protection characteristic of SC4605 power mosfet drivers the SC4605 has two drivers for external power n- mosfets. the driver block consists of one high side n- mosfet, 1a driver, drvh, and one low side 1a, n-mosfet driver, drvl, which are optimized for driving external power mosfets in a synchronous buck converter. the output drivers also have gate drive non-overlap mecha- nism that gives a dead time between drvh and drvl transitions to avoid potential shoot through problems in the external mosfets. by using the proper design and the appropriate mosfets, a 12a converter can be achieved. as shown in figure 2, td1, the delay from the top mosfet off to the bottom mosfet on is adaptive by detecting the voltage of the phase node. td2, the delay from the bottom mosfet off to the top mosfet on is fixed, is 50ns for the SC4605. this control scheme guar- antees avoiding the cross conduction or shoot through between two mosfets and minimizes the conduction loss in the bottom diode for high efficiency applications. bottom mosfet gate drive top mosfet gate drive phase node ground t d1 t d2 figure 2. timing waveforms for gate drives and phase node inductor selection the factors for selecting the inductor include its cost, efficiency, size and emi. for a typical SC4605 applica- tion, the inductor selection is mainly based on its value, saturation current and dc resistance. increasing the in- ductor value will decrease the ripple level of the output voltage while the output transient response will be de- graded. low value inductors offer small size and fast tran- sient responses while they cause large ripple currents, poor efficiencies and more output capacitance to smooth out the large ripple currents. the inductor should be able to handle the peak current without saturating and its copper resistance in the winding should be as low as possible to minimize its resistive power loss. a good trade- off among its size, loss and cost is to set the inductor ripple current to be within 15% to 30% of the maximum output current.
8 ? 2004 semtech corp. www.semtech.com SC4605 power management the inductor value can be determined according to its operating point and the switching frequency as follows: omax s i o i o i i f v ) v v ( v l ? ? ? ? ? ? = where: fs = switching frequency and di = ratio of the peak to peak inductor current to the maximum output load current. the peak to peak inductor current is: omax p p i i i ? ? = ? after the required inductor value is selected, the proper selection of the core material is based on the peak in- ductor current and efficiency requirements. the core must be able to handle the peak inductor current ipeak without saturation and produce low core loss during the high frequency operation. 2 i i i p p omax peak ? + = the power loss for the inductor includes its core loss and copper loss. if possible, the winding resistance should be minimized to reduce inductor?s copper loss. the core loss can be found in the manufacturer?s datasheet. the inductor? copper loss can be estimated as follows: winding lrms 2 copper r i p ? = where: ilrms is the rms current in the inductor. this current can be calculated as follows: 2 omax lrms i 3 1 1 i i ? ? + ? = output capacitor selection basically there are two major factors to consider in se- lecting the type and quantity of the output capacitors. the first one is the required esr (equivalent series re- sistance) which should be low enough to reduce the volt- age deviation from its nominal one during its load changes. the second one is the required capacitance, which should be high enough to hold up the output voltage. before the SC4605 regulates the inductor current to a new value during a load transient, the output capacitor delivers all the additional current needed by the load. the esr and esl of the output capacitor, the loop parasitic inductance between the output capacitor and the load combined with inductor ripple current are all major contributors to the output voltage ripple. surface mount speciality poly- mer aluminum electrolytic chip capacitors in ue series from panasonic provide low esr and reduce the total capacitance required for a fast transient response. poscap from sanyo is a solid electrolytic chip capacitor that has a low esr and good performance for high fre- quency with a low profile and high capacitance. above mentioned capacitors are recommended to use in SC4605 applications. boost capacitor selection the boost capacitor selection is based on its discharge ripple voltage, worst case condition time and boost cur- rent. the worst case conduction time t w can be estimated as follows: max s d f 1 tw ? = where: f s = the switching frequency and dmax = maximum duty ratio, 0.97 for the SC4605. the required minimum capacitance for boost capacitor will be: w d b boost t v i c ? = where: i b = the boost current and v d = discharge ripple voltage with f s = 300kh, v d = 0.3v and i b = 50ma, the required capacitance for the boost capacitor is: nf 540 97 . 0 k 300 1 3 . 0 05 . 0 d f 1 v i c max s d b boost = ? ? = ? ? = input capacitor selection the input capacitor selection is based on its ripple cur- rent level, required capacitance and voltage rating. this capacitor must be able to provide the ripple current by the switching actions. for the continuous conduction applications information (cont.)
9 ? 2004 semtech corp. www.semtech.com SC4605 power management mode, the rms value of the input capacitor can be cal- culated from: i 2 o i o omax ) rms ( cin v ) v v ( v i i ? ? ? = this current gives the capacitor?s power loss as follows: ) esr ( cin ) rms ( cin 2 cin r i p ? = this capacitor?s rms loss can be a significant part of the total loss in the converter and reduce the overall con- verter efficiency. the input ripple voltage mainly depends on the input capacitor?s esr and its capacitance for a given load, input voltage and output voltage. assuming that the input current of the converter is constant, the required input capacitance for a given voltage ripple can be calculated by: ) r i v ( fs ) d 1 ( d i c ) esr ( cin omax i omax in ? ? ? ? ? ? ? = where: d = vo/vi , duty ratio and dvi = the given input voltage ripple. because the input capacitor is exposed to the large surge current, attention is needed for the input capacitor. if tantalum capacitors are used at the input side of the converter, one needs to ensure that the rms and surge ratings are not exceeded. for generic tantalum capaci- tors, it is wise to derate their voltage ratings at a ratio of 2 to protect these input capacitors. power mosfet selection the SC4605 can drive an n-mosfet at the high side and an n-mosfet synchronous rectifier at the low side. the use of the high side n-mosfet will significantly re- duce its conduction loss for high current. for the top mosfet, its total power loss includes its conduction loss, switching loss, gate charge loss, output capacitance loss and the loss related to the reverse recovery of the bot- tom diode, shown as follows: applications information (cont.) s i rr oss s gate gt 2 gs gd g gate s i peak _ top on _ top rms _ top 2 total _ top f v ) q q ( f v q ) q q ( r v f v i r i p ? ? + + ? ? + + ? ? ? + ? = where: rg = gate drive resistor, qgd = the gate to drain charge of the top mosfet, qgs2 = the gate to source charge of the top mosfet, qgt = the total gate charge of the top mosfet, qoss = the output charge of the top mosfet and qrr = the reverse recovery charge of the bottom diode. for the top mosfet, it experiences high current and high voltage overlap during each on/off transition. but for the bottom mosfet, its switching voltage is the bottom diode?s forward drop during its on/off transition. so the switching loss for the bottom mosfet is negligible. its total power loss can be determined by: f avg d s gate gb on _ bot rms _ bot 2 total _ bot v _ i f v q r i p ? + ? ? + ? = where: qgb = the total gate charge of the bottom mosfet and vf = the forward voltage drop of the bottom diode. for a low voltage and high output current application such as the 3.3v/1.5v@12a case, the conduction loss is of- ten dominant and selecting low rds(on) mosfets will noticeably improve the efficiency of the converter even though they give higher switching losses. the gate charge loss portion of the top/bottom mosfet?s total power loss is derived from the SC4605. this gate charge loss is based on certain operating conditions (fs, vgate, and i o ). the thermal estimations have to be done for both mosfets to make sure that their junction temperatures do not exceed their thermal ratings according to their total power losses ptotal, ambient temperature ta and their thermal resistance r ja as follows: ja total a (max) j r p t t + <
10 ? 2004 semtech corp. www.semtech.com SC4605 power management c2 r1 c1 l1 c4 c9 r8 r7 r9 +vo SC4605 vcc 2 iset 3 comp 4 fset 5 bst 1 drvh 10 drvl 8 vsense 6 gnd 7 phase 9 figure 3. compensation network provides 3 poles and 2 zeros. for voltage mode step down applications as shown in figure 3, the power stage transfer function is: 4 1 2 1 4 c i vd c l s r l s 1 c r 1 s 1 v ) s ( g + + ? + = where: r = load resistance and r c = c 4 ?s esr. the compensation network will have the characteristic as follows: 2 p 2 z 1 p 1 z i comp s 1 s 1 s 1 s 1 s ) s ( g + ? + ? + + ? = where; ) c c ( r 1 2 1 7 i + ? = 2 1 1 z c r 1 ? = 9 8 7 2 z c ) r r ( 1 ? + = 2 1 1 2 1 1 p c c r c c ? ? + = 9 8 2 p c r 1 ? = after the compensation, the converter will have the following loop gain: lc s r l s 1 c r 1 s 1 s 1 s 1 s 1 s 1 s v v 1 ) s ( g ) s ( g g ) s ( t 2 4 c 2 p 2 z 1 p 1 z i i m vd comp pwm + + ? + ? + ? + ? + + ? ? ? = ? ? = where: g pwm = pwm gain v m = 1.5v, ramp peak to valley voltage of SC4605 applications information (cont.) loop compensation design for a dc/dc converter, it is usually required that the converter has a loop gain of a high cross-over frequency for fast load response, high dc and low frequency gain for low steady state error, and enough phase margin for its operating stability. often one can not have all these properties at the same time. the purpose of the loop compensation is to arrange the poles and zeros of the compensation network to meet the requirements for a specific application. the SC4605 has an internal error amplifier and requires the compensation network to connect among the comp pin and vsense pin, gnd, and the output as shown in figure 3. the compensation network includes c1, c2, r1, r7, r8 and c9. r9 is used to program the output voltage according to: ) r r 1 ( 8 . 0 v 9 7 o + ? =
11 ? 2004 semtech corp. www.semtech.com SC4605 power management applications information (cont.) the design guidelines for the SC4605 applications are as following: 1. set the loop gain crossover corner frequency c for given switching corner frequency s =2 f s , 2. place an integrator at the origin to increase dc and low frequency gains, 3. select z1 and z2 such that they are placed near o to damp the peaking and the loop gain has a -20db/dec rate to go across the 0db line for obtaining a wide bandwidth, 4. cancel the zero from c 4 ?s esr by a compensator pole p1 ( p1 = esr = 1/( r c c 4 )), 5. place a high frequency compensator pole p 2 ( p 2 = f s ) to get the maximum attenuation of the switching ripple and high frequency noise with the adequate phase lag at c . the compensated loop gain will be as given in figure 4: -20db/dec 0db gvd t z1 z2 p 1 p 2 c esr o loo p g ain t ( s ) power stage g vd (s) -40db/dec figure 4. asymptotic diagrams of power stage and its loop gain layout guideline in order to achieve optimal electrical, thermal and noise performance for high frequency converters, special at- tention must be paid to the pcb layouts. the goal of lay- out optimization is to identify the high di/dt loops and minimize them. the following guideline should be used to ensure proper functions of the converters. 1. a ground plane is recommended to minimize noises and copper losses, and maximize heat dissipation. 2. start the pcb layout by placing the power compo- nents first. arrange the power circuit to achieve a clean power flow route. put all the connections on one side of the pcb with wide copper filled areas if possible. 3. the vcc bypass capacitor should be placed next to the vcc and gnd pins. 4. the trace connecting the feedback resistors to the output should be short, direct and far away from the noise sources such as switching node and switching components. 5. minimize the traces between drvh/drvl and the gates of the mosfets to reduce their impedance to drive the mosfets. 6. minimize the loop including input capacitors, top/bot- tom mosfets. this loop passes high di/dt current. make sure the trace width is wide enough to reduce copper losses in this loop. 7. iset and phase connections to the top mosfet for current sensing must use kelvin connections. 8. maximize the trace width of the loop connecting the inductor, bottom mosfet and the output capacitors. 9. connect the ground of the feedback divider and the compensation components directly to the gnd pin of the SC4605 by using a separate ground trace. then connect this pin to the ground of the output capacitor as close as possible.
12 ? 2004 semtech corp. www.semtech.com SC4605 power management design example 1: 3.3v to 1.5v @ 12a application with SC4605 (nh020 footprint) figure 5. schematic for 3.3v/1.5v@12a with SC4605 application applications information (cont.) figure 6. schematic for 5v/1.5v@12a with SC4605 application design example 2: 5v to 1.5v @ 12a application with SC4605 (nh020 footprint) r3 2.26k c3 4.7u c2 2.2n r1 14.3k c6 150u c7 150u on/off c1 180p r11 100 c14 0.1u on/off r6 1.0 r5 1.0 j1 1 2 3 4 5 6 d2 l1 1.8u c5 22u c4 22u c71 1u m1 c10 330u m2 c12 22u +vin c9 4.7n r8 200 r7 10k r9 11.5k c20 470pf r10 100 +vout j2 1 2 3 4 5 r12 100 gnd tr i m u1 SC4605 vcc 2 iset 3 comp 4 fset 5 bst 1 drvh 10 drvl 8 vsense 6 gnd 7 phase 9 r13 1 r3 2.26k c3 4.7u c2 2.2n r1 14.3k c6 150u c7 150u on/off c1 180p r11 100 c14 0.1u on/off r6 1.0 r5 1.0 j1 1 2 3 4 5 6 d2 l1 1.8u c5 22u c4 22u c71 1u m1 c10 330u m2 c12 22u +vin c9 4.7n r8 200 r7 10k r9 11.5k c20 470pf r10 100 +vout j2 1 2 3 4 5 r12 100 gnd tr i m u1 SC4605 vcc 2 iset 3 comp 4 fset 5 bst 1 drvh 10 drvl 8 vsense 6 gnd 7 phase 9 r13 1 r3 2.8k c3 4.7u c2 2.2n c6 150u r1 14.3k c7 150u r11 100 c1 180p on/off c14 0.1u on/off r6 1.0 r5 1.0 j1 1 2 3 4 5 6 d2 l1 1.8u c5 22u c4 22u c71 1u m1 c10 330u m2 c12 22u +vin c9 4.7n r8 200 r7 10k r9 11.5k c20 470pf r10 100 +vout j2 1 2 3 4 5 r12 100 gnd tr i m u1 SC4605 vcc 2 iset 3 comp 4 fset 5 bst 1 drvh 10 drvl 8 vsense 6 gnd 7 phase 9 r13 1 r3 2.8k c3 4.7u c2 2.2n c6 150u r1 14.3k c7 150u r11 100 c1 180p on/off c14 0.1u on/off r6 1.0 r5 1.0 j1 1 2 3 4 5 6 d2 l1 1.8u c5 22u c4 22u c71 1u m1 c10 330u m2 c12 22u +vin c9 4.7n r8 200 r7 10k r9 11.5k c20 470pf r10 100 +vout j2 1 2 3 4 5 r12 100 gnd tr i m u1 SC4605 vcc 2 iset 3 comp 4 fset 5 bst 1 drvh 10 drvl 8 vsense 6 gnd 7 phase 9 r13 1
13 ? 2004 semtech corp. www.semtech.com SC4605 power management applications information (cont.) design example 3: 3.3v to 1.5v @ 15a application with SC4605 and its typical efficiency characteristics. figure 7. schematic for 3.3v/1 .5v @ 1 5a with SC4605 application efficiency vs load current 0.88 0.89 0.9 0.91 0.92 0.93 3691215 load current (a) efficiency vin=3.3v vo=1.5v r3 2.43k u2 j12 vout 1 vout 2 vout 3 gnd 4 gnd 5 gnd 6 gnd 7 gnd 8 gnd 9 vout 10 vout 11 vout 12 u3 j8 vin 1 vin 2 vin 8 vin 7 gnd 3 gnd 4 gnd 5 gnd 6 c3 4.7u c2 2.2n r1 15.8k c7 470u p n c1 270p c18 0.1u d2 hc2-2r2 2.2u c5 22u c4 22u c17 1u m11 4 x si 7882 vout=1. 5v 15a m12 m22 c10 330u m21 c9 8.2n r8 115 r7 5.62k r9 6.49k r6 1 r5 1 c16 470pf u1 s c 4605 vcc 2 iset 3 comp 4 fset 5 bst 1 drvh 10 drvl 8 vsense 6 gnd 7 phase 9 c12 22u c13 22u c14 22u c11 330u vi n=3. 3v r13 1 r3 2.43k u2 j12 vout 1 vout 2 vout 3 gnd 4 gnd 5 gnd 6 gnd 7 gnd 8 gnd 9 vout 10 vout 11 vout 12 u3 j8 vin 1 vin 2 vin 8 vin 7 gnd 3 gnd 4 gnd 5 gnd 6 c3 4.7u c2 2.2n r1 15.8k c7 470u p n c1 270p c18 0.1u d2 hc2-2r2 2.2u c5 22u c4 22u c17 1u m11 4 x si 7882 vout=1. 5v 15a m12 m22 c10 330u m21 c9 8.2n r8 115 r7 5.62k r9 6.49k r6 1 r5 1 c16 470pf u1 s c 4605 vcc 2 iset 3 comp 4 fset 5 bst 1 drvh 10 drvl 8 vsense 6 gnd 7 phase 9 c12 22u c13 22u c14 22u c11 330u vi n=3. 3v r13 1
14 ? 2004 semtech corp. www.semtech.com SC4605 power management applications information (cont.) design example 4: 5v to 3.3v @ 5a application with SC4605 and its typical efficiency characteristics. figure 8. schematic for 5v/3.3v@ 5a with SC4605 application efficiency vs load current 0.9 0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 12345 load current (a) efficiency vin=5v vo=3.3v r3 2.87k c3 4.7u c2 2.2n c6 150u r1 14.3k c7 150u r11 100 c1 220p on/off c14 0.1u vi n =5v on/off r6 1.0 r5 1.0 j1 1 2 3 4 5 6 d2 etq p 6f2r5 2.5u c5 22u c4 22u c71 1u m1 2 x s i7882 v o u t=3. 3v / 5a m2 c12 22u c9 10n r8 97.6 r7 4.7k r9 1.5k c20 470pf r10 100 j2 1 2 3 4 5 r12 100 gnd tr i m u1 s c 4605 vcc 2 iset 3 comp 4 fset 5 bst 1 drvh 10 drvl 8 vsense 6 gnd 7 phase 9 c10 22u r13 1 r3 2.87k c3 4.7u c2 2.2n c6 150u r1 14.3k c7 150u r11 100 c1 220p on/off c14 0.1u vi n =5v on/off r6 1.0 r5 1.0 j1 1 2 3 4 5 6 d2 etq p 6f2r5 2.5u c5 22u c4 22u c71 1u m1 2 x s i7882 v o u t=3. 3v / 5a m2 c12 22u c9 10n r8 97.6 r7 4.7k r9 1.5k c20 470pf r10 100 j2 1 2 3 4 5 r12 100 gnd tr i m u1 s c 4605 vcc 2 iset 3 comp 4 fset 5 bst 1 drvh 10 drvl 8 vsense 6 gnd 7 phase 9 c10 22u r13 1
15 ? 2004 semtech corp. www.semtech.com SC4605 power management m e t iy t qe c n e r e f e re u l a vr e r u t c a f u n a m / . o n t r a p 111 cf p 0 8 1 212 cf n 2 . 2 313 c5 0 8 0 , f u 7 . 4 411 7 cf u 1 53 2 1 c , 5 c , 4 c0 1 2 1 , f u 2 2m 6 2 2 j 0 r 5 x 5 2 2 3 c : n / p k d t 62 7 c , 6 c0 7 8 2 , f u 0 5 1l m 0 5 1 b p t 4 : n / p o y n a s 719 cf n 7 . 4 810 1 c0 7 8 2 , f u 0 3 3l m 0 3 3 b p t 6 : n / p o y n a s 914 1 cf u 1 . 0 0 110 2 cf p 0 7 4 1 112 d3 2 1 - d o s , 1 t l 0 2 5 0 r b mr o t c u d n o c i m e s n o 4 111 lf u 8 . 1 , r o t c u d n i : n / p . c i n o s a n a p r f b 8 r 1 f 6 p q t e 5 12 2 m , 1 m8 - o s , k c a p r e w o pp d 8 5 8 7 i s : n / p y a h s i v 6 111 rk 3 . 4 1 7 113 rk 2 3 . 2 8 12 6 r , 5 r0 . 1 9 117 rk 0 1 0 218 r0 0 2 1 219 rk 5 . 1 1 2 23 2 1 r , 1 1 r , 0 1 r0 0 1 3 213 1 r1 4 211 u5 0 6 4 c sr t s m i 5 0 6 4 c s : n / p h c e t m e s . e g a k c a p 3 0 6 0 h t i w n o i s i c e r p % 1 e v a h s r o t s i s e r l l a , d e i f i c e p s s s e l n u . e g a k c a p 3 0 6 0 h t i w n o i s i c r e p % 0 2 e v a h l l i w s r o t i c a p a c . s e s a c t u p t u o t n e r e f f i d r o f s e u l a v f o s d n i k 3 e r a e r e h t , 9 r r o f bill of materials - 3.3v to 1.5v @ 12a
16 ? 2004 semtech corp. www.semtech.com SC4605 power management pcb layout - 3.3v to 1.5v @ 12a top top bottom bottom
17 ? 2004 semtech corp. www.semtech.com SC4605 power management over current protection characteristic of SC4605 for 3.3v to 1.5v @12a application the over current protection curve below is obtained by applying a gradually increased load while the load current and the output voltage are monitored and measured. when the load current is increased from 0 to 16.2a (over current trigger point), the output voltage is 1.5v, corresponding from point a to point b. as the load current in- creases further from 16.2a to 16.3a, the output voltage drops significantly from 1.5v (point b) to 0.88v (point c). because an over current and a lower output voltage (0.88v<68.75%*1.5v=1.03v) are present at point c, the SC4605 enters its hiccup mode. then the locus of the output current and the output voltage follows line cd as shown in the curve. due to the over current applied, the hiccup protection will go back and forth on line cd. this prevents excess power dissipation in the top mosfet during a short output condition. applications information (cont.) ove r cu rrent protection 0 0.5 1 1.5 2 2.5 3 0 5 10 15 20 io (a) vo (v) b c d a ove r cu rrent protection 0 0.5 1 1.5 2 2.5 3 0 5 10 15 20 io (a) vo (v) b c d a
18 ? 2004 semtech corp. www.semtech.com SC4605 power management typical characteristics oscillator internal accuracy vs temperature 298 300 302 304 306 308 310 312 314 -40-200 20406080100120 temperature (c) internal accuracy (khz) vcc = 5v oscillator internal accuracy vs input voltage 304 306 308 310 312 314 316 318 2.5 3 3.5 4 4.5 5 5.5 vcc (v) internal accuracy (khz) ta = 25c sense voltage vs input voltage 0.801 0.802 0.802 0.803 0.803 0.804 2.533.544.555.5 vcc (v) sense voltage (v) t a = 25c sense voltage vs temperature 0.792 0.794 0.796 0.798 0.800 0.802 0.804 -40 -20 0 20 40 60 80 100 120 temperature (c) sense voltage (v) vcc = 5v current limit bias current vs input voltage 47.5 48.0 48.5 49.0 49.5 50.0 50.5 51.0 2.5 3 3.5 4 4.5 5 5.5 vcc (v) current limit bias current (ua) t a = 25c current limit bias current vs temperature 30.0 35.0 40.0 45.0 50.0 55.0 60.0 -40 -20 0 20 40 60 80 100 120 temperature (c) current limit bias current (ua) vcc = 5v
19 ? 2004 semtech corp. www.semtech.com SC4605 power management outline drawing - msop-10 semtech corporation power management products division 2oo flynn road, camarillo, ca. 93012 phone: (805)498-2111 fax (805)498-3804 contact information land pattern - msop-10 bbb c a-b d dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- notes: 1. 2. -a- -h- side view a b c d h plane 0 .010 .004 - .016 .003 .024 (.037) - .000 .030 - - - - 0.25 0.10 8 0 - 8 0.60 (.95) .032 .009 0.40 0.08 .043 .006 .037 0.75 0.00 - 0.80 0.23 - 0.95 1.10 0.15 - - - e .193 bsc .020 bsc detail aaa c seating indicator ccc c 2x n/2 tips pin 1 2x e/2 10 see detail a1 a a2 bxn d 0.25 a plane gage .003 e1 12 n .114 .114 .118 .118 .007 - 10 01 c (l1) l a 0.08 3.00 3.00 4.90 bsc 0.50 bsc .122 .122 2.90 2.90 .011 0.17 3.10 3.10 0.27 - reference jedec std mo-187 , variation ba. 4. dim ccc a1 e bbb aaa 01 l1 n l d e1 e a2 b c a millimeters nom inches dimensions min nom max min max e this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. p (c) x z g y .063 .224 .011 .020 .098 (.161) 5.70 1.60 0.30 0.50 2.50 (4.10) millimeters dimensions dim inches y z g p x c

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